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The self-aligned HARPSS fabrication process offers the possibility of the sub-micron capacitive HARPSS gap together with several self-align gaps.
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Background: The self-aligned HARPSS fabrication process offers the possibility of the sub-micron capacitive HARPSS gap together with several self-align gaps, which were not available using the conventional HARPSS. Using this new fabrication process, several large-value, low-voltage, two-port tunable capacitors are reported. With a capacitive gap of 800nm and an aspect-ratio of 87, a maximum tuning of 240% was observed for a 15pF two-port tunable capacitor fabricated on a 70um thick SOI substrate. Using the proposed fabrication, the aspect-ratio of such devices can easily be extended to more than 200, yielding much larger-value capacitors in the same die area.