Network On Chip (NoC) Analysis

About

About The tool comprises of a clock cycle accurate model of the whole network, including routers, switches, vertical links (TSVs), buffers and routing wires and is developed for performance and energy evaluation for any 3D NoC architecture, especially irregular (heterogenous) network architectures. In addition, various routing algorithms, traffic patterns and rates, NoC dimensions, topologies and mapping algorithms are included in the tool for comprehensive evaluation of homogenous and heterogenous 3D NoCs, in terms of average packet latency and total energy consumption. The image demonstrates the tools unique feature of extracting link and buffer utilisation of the target application, allowing the designer to further improve and tailor the NoC architecture for specific applications. The tool is equipped with a Graphical User Interface (GUI), which provides a real-time graphical update of NoC performance metrics and simulation progress for a given configuration. Also embedded in the simulation framework are algorithms to automatically generate log files of various evaluation parameters such as average link (and buffer) utilisation of each node and traffic traces files of various networks. The simulator is compatible with both Orion and Ebit energy models for power and energy consumption estimates.   Key Benefits Multiple layer chip analysis Novel optimisation techniques in terms of link and buffer utilisation Flexibility in evaluating both irregular arrangements of vertical links as well as partial vertical links   Applications High-performance computing systems Low power electronic computing systems Computationally intensive parallel systems Safety critical applications   IP Status The technology is protected by a UK patent application. The university is seeking commercial partners interested in developing, licensing or exploiting this technology.