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Fabrication that is simple, high-yield, high-volume and CMOS-compatible and the microscanners that are high performance and low cost.
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Summary MEMS scanners that are vertically offset have the potential to be used in a variety of innovative applications. However, these microscanners have several fabrication challenges that make them cost prohibitive for most commercial uses. These fabrication difficulties include the need for: (a) a two-wafer process for the critical-alignment step, (b) the control and replication of the properties of materials such as photoresist or bi-morph layers (when they are used for hinges), (c) a post-process-annealing in a high-temperature furnace following the hand assembly of lid and device chips, and (d) the creation of offset combs by depositing multiple-masking layers (composed of silicon dioxide and silicon nitride). To address these fabrication issues, researchers at UC Berkeley have developed an innovative process for fabricating torsional microscanners with vertically offset interdigitated-comb actuators. This improved and simplified CMOS-compatible process uses SOI wafers and offers excellent yields with high performance attributes. These new microscanners have been built with resonant frequencies between 108 Hz and 24 KHz, maximum optical-scanning angles of 70 degrees, and actuation voltages from 10-72.8V.