High-Speed Clock

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Summary: High-speed data streams can be sent without an accompanying clock signal, where the receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a phase-locked loop (PLL). This process is commonly known as clock and data recovery (CDR). CDR circuits operating at tens of gigabits per second pose difficult challenges with respect to speed, jitter, signal distribution, and power consumption. Half-rate 40-Gb/s CDR circuits have been implemented in bipolar technology but require large voltage supplies and draw high amounts of power. On the other hand, the recent integration of 10-Gb/s receivers in CMOS technology encourages further research on CMOS solutions for higher speeds, especially if it enables low-voltage, low-power realization.       Innovation: To solve these problems, researchers at UCLA have invented a 40-Gb/s phase-locked CDR circuit fabricated in 0.18-µm CMOS technology. This is achieved by incorporating a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals.      Applications: Phase-locked clock and data recovery circuits for high-speed data transmission.   Advantages: Capable of 40-Gb/s operation  Dramatically low supply voltage needed and extremely low power dissipation