Differential Logic Devices.

About

Technology Cornell researchers have developed high speed logic gates that operate at significantly lower supply voltage while offering performance comparable to current mode logic (CML). The fastest digital circuits are currently implemented in CML, which is based on stacked differential pairs and requires a supply voltage of 3.3 to 5V for bipolar technologies. Cornell's new topology reduces current logic device stacking from three levels to two levels. Combined with similar bias current requirements and depending on the logic function it can provide power savings of 25 to 50% at supply voltages as low as 2V. The low-voltage logic gates consist of single-level differential pairs driving emitter followers, which can be connected in parallel or selectively switched. Consequently, every logic operation is initiated in the current domain using differential pairs and completed in the voltage domain using emitter followers. Advantages Enables single ended or differential inputs circuits, reduced levels of stacked active circuit elements from 3 to 2, lower supply voltage requirement, as low as 2V, making it compatible with current semiconductor scaling trends, and simplifies the integration of high-speed logic cores with other parts of a system, less real estate required on chip and board levels due to smaller reference voltage differences, reduced power consumption of 25% - 50%, or more (depending on the logic function), generates less heat, reduces need for heat dissipation via e.g., heat sinks and liquid cooling, fast, switching speeds of 40 GHz, achieved data rates up to 100-120Gb/s and improved radiation hardness.