Circuit Integration

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Summary: UCLA researchers in the Department of Electrical Engineering have developed and reduced-to-practice a CMOS architecture that will improve the performance and reduce the cost of three-dimensional integrated circuits.   Background: The demand for higher performance, lower power and lower cost semiconductor chips, has driven new methods for chip design. Due to physical constraints, the current planar integrated circuit technology is not able to handle all of these demands. Three-dimensional integrated circuits (3D ICs) design technologies mitigate current physical constraints, but continue to pose manufacturing/cost challenges.Current methods for connecting vertical active device layers in 3D ICs involves etching which is complex, costly, and interferes with circuit performance. Alternative techniques involving RF interconnects have significant power consumption and design overhead. An efficient vertical interconnection is a key technology to realize future 3D ICs.    Innovation: Researchers at UCLA have developed an innovative method to transmit and receive signals between active device layers. The technology is called a Self-Synchronized RF-Interconnect (SSRFI). The active device layers are connected through an AC coupling methodology. By removing the need for etching interconnect vias, the 3D IC fabrication process cost is reduced and yields are improved. This novel method outperforms other RF connects that require additional overhead circuitry. The result is reduced design complexity, power consumption, chip area, and improved signal integrity.    Advantages: Requires less power than alternative methods. AC coupling eliminates DC power consumption  Cost and complexity of production are reduced. Complex etching is unnecessary since AC coupling scheme does not require via etching.  A high-speed interconnect with improved signal integrity.