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Technology # 18-05 A method for Chip Warpage Reduction
About
Technology # 18-05 A method for Chip Warpage Reduction A key challenge in microelectronic assembly arises when chip warpage, resulting from thermal expansion mismatch in layered materials, drives incompatibility in assembly, and can result in interfacial stresses when experiencing temperature swings native to device operation. Currently, linear copper structures are used to deliver current and signals to and from the active elements in the device. The layout and direction of these are directly related to the warpage that is demonstrated and often have to be balanced in the design in attempt to homogenize the warpage. This invention/technology is available for licensing. For interested parties seeking further information, feel free to contact: Mark Allen Lanoue Technology Manager / Tech Ventures University of Arkansas (479) 575-7243 [email protected]
Key Benefits
Advantage(s): 50.78% reduction in warpage, improved yield in flip-chip assembly, reduced stresses for improved component reliability
Applications
Application(s): Cell phones, processors, micro-controllers, computers, power electronics, MEMS devices, sensors and micro-antennae Other Technology: A new methodology exists to increase trace freedom, relieving pressure due to thermal expansion. The results of this method have demonstrated 50.78% reduction in warpage, leading to improved yield in flip-chip assembly, and reduced stresses for improved content reliability. Additionally, the reduction in warpage is expected to impact interfacial stresses in such a way that extended lifetimes are made possible through reduction in thermo-mechanical fatigue.