Arrays for Memory and Logic

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Track Code 2009-039 Short Description The methods and artifacts associated with the design of high density embedded memory, such as SRAM and DRAM, on the extreme regular patterning that will be required at scaled silicon technologies, that further enables the implementation of logic and other non-memory circuit functions on a shared number of front-end-of-line (FEOL) process layers. As an example, FEOL patterns for embedded memory that consist of diffusion, polysilicon, and contact patterns to form dense SRAM circuits with double patterning are reconfigured with an e-beam starting with the 2nd patterning step for polysilicon to configure logic instead of high density memory. Part of this invention includes the co-optimization of FEOL memory patterns to achieve memory density and performance while providing enough adjustability to achieve sufficient logic.   Competitive Advantage This invention of regular-pattern arrays for memory and logic could provide an attractive option for low volume integrated circuits at the most advanced technology nodes that require quick time to market and affordable NRE expenses.