Simulating On-Chip RLC

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Brief Description: This is a technique to simulate the on-chip transient output response of a distributed RLC interconnect.  The method is based on direct pole extraction of an exact transmission line transfer function.   Closed form expressions of the poles are developed for the zero driver resistance case. To utilize these expressions, an interconnect system with a driver resistance is converted to a system without a driver resistance.  Based on these poles, closed form expressions for the step and ramp responses are determined.  Applications: The technique is used in CMOS chip design.    Advantages: With increasing on-chip signal frequencies, the effect of interconnect inductance has become significant and the timing characteristics of  signals need to be determined and controlled precisely.   The invention describes an accurate and efficient solution for the transient response at far end of a transmission line. The technique is based on direct pole extraction of the exact transmission line transfer function rather than obtaining the poles of a truncated transfer function as proposed elsewhere.  With two pairs of poles, the method provides an accurate delay estimate, exhibiting an average error of 1% as compared to Spectre simulations. Higher accuracy can be obtained with additional poles. A trade-off between accuracy and efficiency is provided in this approach.   The computational complexity of the model is however proportional to the number of pole-pairs that are included in the calculation.  The average error in delay, rise-time and over-shoots are considerably less than those in the Spectre simulations.  Frequency dependent effects are also successfully included in the method and excellent match is observed between the proposed model and Spectre simulations.